A. Field of the Invention
The invention relates to the field of architecture of Very Long Instruction Word (VLIW) processors.
B. Related Art
The invention is an improvement on U.S. application Ser. No. 08/445,963 filed May 22, 1995, now abandoned, (PHA 21,777a) which is incorporated herein by reference.
Prior art VLIW processors can be as shown in FIG. 1. They are characterized by having an instruction issue register (IIR) 104 having a plurality of issue slots. Each issue slot is for containing a respective operation. All of the operations which are held simultaneously in the instruction issue register are to be begun in a same machine cycle. Each operation is to be executed on an appropriate one of the functional units FU1, FU2, . . . , FUN. The operations are RISC-type operations, in that an operation can be begun in each machine cycle for each slot of the IIR.
The VLIW processor includes a multiport register file 101. This multiport register file 101 stores operands destined for the functional units FU1, FU2, . . . , FUN and results produced by the functional units.
A read crossbar 102 directs operands from the multiport register file 101 to appropriate ones of the functional units FU1, FU2, . . . , FUN under control of signals from the instruction issue register 104.
A write control unit 103 governs timing of writing of results from the functional units FU1, FU2, . . . , FUN to the multiport register file 101.
It is a disadvantage of the prior art that the read crossbar 102 takes up a lot of real estate on the processor chip.